Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this disclosure and are not admitted to be prior art by inclusion in this section.
Typically, there are two power control loops, i.e., the inner loop and the outer loop. The inner loop power control is used to continuously adjust transmission power such that the perceived quality is sufficient and adequate but not excessively good. It may be employed in both uplink and downlink. Specifically, in the uplink, it is the dedicated physical control channel (DPCCH) power that is actually controlled by the inner loop power control based on the comparison of the perceived uplink DPCCH quality with the uplink DPCCH quality target, while the power offset between the data channel(s) and DPCCH is not changed by the power control. For example, the DPCCH quality here may refer to DPCCH Signal to Interference plus Noise Ratio (SINR). A lower DPCCH power might somewhat impact the channel estimation, but usually the penalty is very limited.
The outer loop power control adjusts the DPCCH quality target used for the inner loop power control. Such an adjustment is based on the perceived error rate of the data part. This implies that the overall power control including both the inner loop power control and the outer loop power control adjusts the quality for both pilot (DPCCH) and data jointly just based on the data quality.
When an advanced receiver such as an interference cancellation (IC) receiver is used at the base station the perceived interference after the cancellation can substantially be decreased by “soft” symbols regeneration and cancellation, and the received SINR at the BS after IC can be significantly improved. This results in that an evident improvement in uplink data rate can be achieved. Both data channel (e.g. E-DPDCH) and control channel (e.g. DPCCH) can benefit from IC. However, it should be noted that the first initial channel estimate based on only DPCCH must be good enough to start the whole IC process, and that the channel estimate is before any IC. This is because with a poor channel estimation the regenerated signal that is cancelled will deviate from the true received signal. Thus, the DPCCH quality must be good enough and a bad DPCCH quality can negatively impact the benefit we can get from IC.
FIG. 1 illustrates the level of interference that can be cancelled from DPCCH and E-DPDCH with multi-stage IC. Lower residual interference fraction (RIF) value means less interference remains after IC. It can be seen from FIG. 1 that if DPCCH SINR before IC is not high enough (e.g., <7 dB), the residual (remaining) interference after IC due to E-DPDCH will quickly increase and there will be less benefit of using IC. Therefore, ensuring better DPCCH quality before IC is of particular importance.
For example, with turbo-IC, there is a new dependence between the users. That is, the reduced received power of one user may lead to higher residual interference and worse performance of the other user(s). A well known example of an advanced receiver is a Minimum Mean Square Error Interference Rejection Combining (MMSE-IRC). An example of a more sophisticated advanced receiver is Mean Square Error-turbo Interference Cancellation (MMSE-turbo IC) capable of performing nonlinear subtractive-type interference cancellation, which may be used to further enhance system performance.
It should be noted that the terms “interference mitigation receiver”, “interference cancellation receiver”, “interference rejection receiver”, “interference aware receiver”, “interference avoidance receiver”, etc. may be interchangeably used here since they all belong to a category of an advanced receiver or an enhanced receiver. All these different types of advanced receiver may improve respective performances by fully or partly eliminating the interference arising from at least one interfering source. The embodiments of the present invention are applicable for any type of advanced receiver used in the base station.
Since the power control loops only consider the performance of a single user, there is a risk that the decreasing of DPCCH quality target (by the outer loop power control) and/or of the UE transmit power (by the inner loop power control) can have a negative effect on other users. This is undesirable especially in terms of the cost, complexity and processing (impacting power consumption, delay, etc.) associated with implementing IC. In this case, it may be better to keep or increase the pilot (DPCCH) power but decrease the data power instead. However, in WCDMA/HSPA, it is impossible to control pilot and data power independently with the power control.
For the above mentioned problems about the current transmit power control, it is needed to design a method to overcome them so as to control the transmit power more effectively.